Developments in integrated circuit technology have often focused on improving the integration density of various electronic components, such as transistors, capacitors, diodes, resistors, and inductors, into a given chip or wafer area. Various improvements have involved the reduction of minimum component size, permitting more components to be integrated on the surface of the semiconductor die. Such two-dimensional (2D) integration density improvements are physically limited by device size, the size of the die, and other limitations including the complexity of design, such as, for example, the requisite length and number of interconnections between devices, and the corresponding circuit delay and power consumption increases.
Three-dimensional integrated circuits (3D-IC) and stacked wafers or dies are used to resolve some of the limitations of 2D integrated circuits. Plural dies are stacked vertically within a single package and electrically connected to each other. Through substrate vias (also referred to as through silicon vias), TSVs, are often used in stacked wafer/die packaging structures to connect the wafers or dies in 3D-IC structures. TSVs are vertical openings passing completely though semiconductor substrates and filled with conductive material to provide connections between stacked wafers or dies, or between front and back surfaces of a die. The total interconnect length of the integrated circuits has been found to decrease as the number of dies or wafers increased in the 3D stack.